Guys..
I am *brand new* to Aldec Active HDL. What few
cpld/pals that I have done have been with CUPL.
I've started using ActiveHDL(Student Ver), writing some easy VHDL
just to get acquainted with both VHDL and the Aldec tool.
What I don't understand is the integrated implementation
****tion. If I were to want to do a Altera design, for example,
do I need to have the Altera toolset installed in order to
build the jedec file or does the Aldec tool do that also?
I guess I am at a loss at the point between designing/simulating the
project and implementation with ActiveHDL.
Help me see the light.
Thanks,
Jim
