Goli wrote:
> hi,
>
> I am looking for connecting my proprietary 8 bit bus interface across
> two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
> to use differential as that would take lot of pins, Is there any
> single ended interface that I can use. I dont think LVTTL and LVCMOS
> would work at such high speeds, whereas HSTL kind of interfaces can
> not drive that long a trace.
>
> So is there any other IO standard that I can use for this?
If you were trying to run at 210 MHz, I'd see where you might need to be
more careful. You can use virtually any logic standard to get 70 MHz
operation over 10 inches.
Since you're point-to-point, I'd suggest using source-series termination
which is simply adding a resistor to your front end so your driver
impedance plus resistor roughly matches the characteristic impedance of
your PC board trace. Simon mentioned you need a ground plane; to get a
good impedance without huge crosstalk and other problems, the ground
plane is integral to any solid design driven with high edge-rate signals.
When you drive a source-terminated signal to VCCIO, the source impedance
looks like a resistor divider into the instantaneous load of the
transmission line that's about 2ns long on your PC board. While a
half-amplitude signal may seem bad conceptually, when the signal reaches
the nearly open end of the PC trace, the voltage level doubles as a
reflection heads back to the driver. When the reflection finally hits
the driver 4ns after the signal starts driving, the voltage level
establishes to right around VCCIO with little or no drive current, hence
minimal further activity on the line. If you used a heavy drive current
without a resistor, the reflection would be much higher than VCCIO and
the driver's protection diode would have to swallow a large amount of
current for 4ns (round trip time). Not recommended.
A single resistor is cheap and easy. LVCMOS and LVTTL give you a broad
choice of drive currents. If you wanted to look through the IBIS models
for the "best" source impedance match to your PC trace and even *skip*
the source series resistor, you'd work well. The tolerance on the drive
current at half voltage is sloppy enough that driving harder with a
series resistor gives you a more consistent source impedance.
Once you get the basics of source series terminations under your belt,
the use can be quick and easy in future designs and your signal fidelity
will thank you. If you probe this signal to see what it looks like, do
so as close to the receiver pin as possible since you'll see the full
voltage swing there rather than a couple inches away where you'll see
the incident 1/2 voltage before the reflection brings the voltage back
to VCCIO.
If you use a multi-drop bus instead, this approach is not advised
without further investigation and simulation. For a bidirectional bus,
the approach is still valid with the series resistor on each end. An
open with a series resistor still looks pretty much like an open. The
RC time constant of your receiver will be higher but you're talking a
very few pF parasitics into a resistor typically 22-49 ohms; both
directions look like source series terminated signals.
This stuff is great.
I would have *no* qualms running a 200 MHz TTL bus with properly
selected termination schemes.
- John_H
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