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Re: Single ended interface at 70Mhz for FPGAs

by Goli <togoli@[EMAIL PROTECTED] > Jul 6, 2008 at 10:46 PM

On Jul 5, 12:47 am, Jim Granville <no.s...@[EMAIL PROTECTED]
>
wrote:
> Goli wrote:
> > hi,
>
> > I am looking for connecting my proprietary 8 bit bus interface across
> > two Xilinx FPGAs across the back plane, (10 inch trace). I dont want
> > to use differential as that would take lot of pins, Is there any
> > single ended interface that I can  use. I dont think LVTTL and LVCMOS
> > would work at such high speeds, whereas HSTL kind of interfaces can
> > not drive that long a trace.
>
> > So is there any other IO standard that I can use for this?
>
> Does this have to pass any EMC tests ?
> Will you need any headroom, or will the Bus NEVER
> be faster than 70Mhz ?
> There are also 4 bit busses : The intel LPC and QuadSPI
> use fewer pins.
>
> -jg

This is proprietary bus and it would not run greater than 70Mhz, but
it is bi-directional bus.
--
Goli
 




 7 Posts in Topic:
Single ended interface at 70Mhz for FPGAs
Goli <togoli@[EMAIL PR  2008-07-04 04:10:43 
Re: Single ended interface at 70Mhz for FPGAs
nico@[EMAIL PROTECTED] (  2008-07-04 15:48:57 
Re: Single ended interface at 70Mhz for FPGAs
"Symon" <sym  2008-07-04 18:10:12 
Re: Single ended interface at 70Mhz for FPGAs
Jim Granville <no.spam  2008-07-05 07:47:50 
Re: Single ended interface at 70Mhz for FPGAs
"MM" <mbmsv@  2008-07-04 16:48:30 
Re: Single ended interface at 70Mhz for FPGAs
John_H <newsgroup@[EMA  2008-07-05 09:18:06 
Re: Single ended interface at 70Mhz for FPGAs
Goli <togoli@[EMAIL PR  2008-07-06 22:46:10 

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