On Jul 5, 3:43 am, Zhane <m...@[EMAIL PROTECTED]
> wrote:
> On Jul 4, 11:38 pm, Mike Treseler <mtrese...@[EMAIL PROTECTED]
> wrote:
>
> > Zhane wrote:
> > > # ** Warning: Design size of 11167 statements or 0 non-Xilinx leaf
> > > instances exceeds ModelSim XE-Starter recommended capacity.
>
> > Why does it take 11,167 statements to describe a fifo?
> > Seehttp://mysite.verizon.net/miketreseler/sync_fifo.vhd
>
> no idea
> I used the Core generator to generate
> and used the structural one to simulate
> and end up getting that error
It is not an error, only a warning. It does not prevent you from
simulating
the design. It only states that your license type will force ModelSim
to run very slowly. However I think this has nothing to do with your
problem simulating.
What do you mean by "there doesnt seem to be
any data coming out of my FIFO during the clock cycles"? Can you look
at the simulation and see that the data is going in to the
FIFO and the write enable is active? Does the FIFO become non-empty
and read enable asserted? Have you dealt with the global reset
for the core model? Perhaps it's always being held reset?
Regards,
Gabor
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