biff wrote:
> On Jul 1, 10:01 pm, Tim Wescott <t...@[EMAIL PROTECTED]
> wrote:
>> biff wrote:
>>> Hi folks,
>>> I manage a hardware engineering group for a telcom company and I am
>>> beginning to look around for FPGA IP to implement both FSK modulation
>>> and demodulation. I am wondering if any of you have any experience
>>> with any of the IP around today. The demodulator is the most difficult
>>> part and I believe the following list of requirements is fairly close:
>>> * 300 KHz bandwidth
>>> * 5-21 MHz frequency range
>>> * bit rate = 39.4 KHz
>>> * modulation FSK, Äf = 75 kHz ± 10 KHz, fMark = fc+Äf, fSpace = fc-Äf
>>> The modulator would have similar requirements. Any suggestions would
>>> be appreciated. My shop uses both Xilinix and Altera. While we are
>>> most comfortable with FPGAs, a DSP would also be a possibility if good
>>> software is available.
>>> If you think that IP would not be the best choice and another approach
>>> would be better, feel free to make a suggestion.
>>> Biff
>> FSK is pretty easy. This is an elementary enough problem that by the
>> time you finish evaluating IP and integrating it into your design
you've
>> spent more money than you would just designing it, or hiring it done
>> custom for you.
>>
>> So I suspect that no one bothers making IP for it.
>
> Hiring someone would be an option.
>
>> From your specs I gather that you aren't looking for coherent
>> demodulation. Are you looking at a nice clean signal going into the
>> FPGA, or are you coming off of ADCs and wanting to get near-optimal
>> detection?
>
> The incoming signal is between 10 and 50 dBmV off of a 75 ohm coaxial
> cable (cable TV application). In general the SNR is >20 dB. So the
> signal is large and fairly clean. I am looking for suggestions on what
> to do. My primary focus right now is getting an estimate of the amount
> of effort associated with this development so I can put together a
> proposal. This includes an estimate of the some of the basic FPGA
> requirements. Things like sample rate, quantization, etc.
>
"Lots". There, isn't that helpful? This is definitely a 'devil's in
the details' sort of problem, so whether you need lots of hours, lots of
days or lots of weeks depends (ehem) lots on those details.
Is the FSK signal to all other energy better than 20dB, or does the FSK
signal have to be filtered out from the background? Is the carrier
frequency known ahead of time? How close are any other interfering
signals?
I assume that you'll want to have some sort of sample -> bandpass filter
-> heterodyne -> demodulate -> data slice architecture. If you want to
do it all digitally and you have to go up to 21MHz that implies sampling
well above 42MHz -- 60 would probably be a practical minimum, but you
could save money on your anti-aliasing filter by going higher. You'll
have a lot of gain in the bandpass filter, so there's a chance that you
can do this with a low-bit-count ADC -- the answer to that question
depends on more information than you've given, although if the FSK
signal were the _only_ signal on the wire then you could do it with a
comparator.
--
Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" gives you just what it says.
See details at http://www.wescottdesign.com/actfes/actfes.html
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