Hi Folks,
I've been getting acquainted with the SHARC 21369 the last few days and
have some questions on its memory architecture:
1. Is the basic idea a sort of crossbar switch in which the three
buses, DM, PM, and IOP, are connected with the four parallel memory
spaces ("blocks" in ADI's parlance) in as parallel a manner as
possible? E.g., if a data value, program value, and I/O value are
required from three different blocks, access can occur in one cycle
(using internal memory)?
This concept is illustrated nicely in Figure 5-1 of the "ADSP-2136x
SHARC Processor Programming Reference",
http://www.analog.com/static/im****ted-files/processor_manuals/ADSP_2136x_PGR_rev1-1.pdf
2. These four "blocks" or memory spaces are defined explicitly for
internal memory (see the datasheet for the internal memory layout). It
also appears that they are implemented via the MS{0,1,2,3} strobe
signals in the external memory interface. Is this correct?
3. Is it true that any of code, data, or IO can reside in any of the
four blocks? For example, ADI suggests that internal memory block 0 be
used for program memory and block 1 for data memory, but in reality
these blocks can be mapped in any way desired. The only caveat is that
if simultaneous I/O / program / data access is required within a
block, extra cycles will be required for the access. Is this correct?
4. What exactly is the "Super" in SHARC? Steven W. Smith (et al.)
states in http://www.dspguide.com/ch28/3.htm
that it is the use of an
instruction cache and I/O controller along with the data and program
memory buses of the standard Harvard architecture.
However, from Figure 5-1 above and the associated text, it appears
that it is the "crossbar switching" of program, data, and IO bus
accesses to each of the four blocks.
Which is correct?
--Randy
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