http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/ $ en-us Copyright 2003-2005, Talk About Network. All Rights Reserved. 2008-12-01T16:12:10+00:00 TAN rss@talkaboutnetwork.com Discussion hourly 1 1970-01-01T00:00+00:00 http://tan12.talkaboutnetwork.com/images/spacer.gif http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/ http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73841.html Hi, following entity should divide a 50 MHz clock into 8khz, 2Hz and 1 Hz. In principle it would work, but 2 Hz clock is 1 Hz and the duty cycle ist about 30/70. If I check Q23 is OK but Q24 and Q25 not. In RTL view the implementation of Q24 and ... Volker ltjreeg@[EMAIL PROTECTED] gt Discussion 2008-12-01T15:15:50+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73831.html Hi, I have some basic question about data types in vhdl. I hope you can give me an answer. Which library should I use in new designs (numeric_std or std_logic_unsigned)? The unsigned type is a vector type? Thank your for your answer. bye martin... Martin Sauer ltmsau@[EMAIL PROTECTED] gt... Discussion 2008-12-01T08:29:46+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73830.html Hello, I am having problem with a VHDL code, simulation was correct, but when synthsized with synplify pro one port is connect, when i saw RTL view . code is shown below entity pn_clk is port( clk: in std_logic ref_clk : in std_logic reset : in st... J.Ram ltjrgodara@[EMAIL PROTECTED] gt Discussion 2008-11-30T21:05:01+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73820.html Hello group, Im learning to write a testbench so in part of the code I increment a variable to count number of errors during simulation. now, I need to know how I can print out a message showing number of detected errors as following: Found n erro... Amit ltamit.kohan@[EMAIL PROTECTED] gt Discussion 2008-11-30T02:21:04+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73817.html Hello, I have a VHDL project which is implemented in a Virtex5. This Virtex5 is connected to a LAN chipset. I use this system to communicate with a PC, and more precisely this system gets many 32-bits parameters. And here is the problem: such a h... =?ISO-8859-15?Q?Fr=E9d=E9ric_Lochon?= lt... Discussion 2008-11-29T15:16:38+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73813.html Which freeware is recommended to use for experiments and and simple tests of designing with VHDL in Linux? Bengt T ltbengt.tornq@[EMAIL PROTECTED] ... Discussion 2008-11-28T11:16:04+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73810.html I have submitted the following article from the New York Times to stimulate interest and activity. November 25, 1999 WHATS NEXT When a Gizmo Can Invent a Gizmo By ANNE EISENBERG IF Dr. Frankensteins monster had published a best seller, who would ha... iajzenszmi@[EMAIL PROTECTED] Discussion 2008-11-27T11:00:04+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73803.html Hi, I found several posts about array indexing but I am still confused on how to use an one-hot address to index the array. The reason why I want o use a hot-one address is that I have to generate the addresses myself in another part of the project ... tudelftrocks@[EMAIL PROTECTED] Discussion 2008-11-26T08:00:09+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73801.html Hi, I found several questions posted about array indexing but I am still confused on how can I solve my problem. I have a memory array that I want to index with a hot-one address. library ieee use ieee.std_logic_1164.all use ieee.std_logic_unsigned... Filipa ltf.duarte@[EMAIL PROTECTED] gt Discussion 2008-11-26T07:43:26+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73796.html Hi there, I hope someone on this group can explain the reason for what Im seeing, for me it does not make any sense... I have an output port that is defined like this, (other ports and signals left out for simplicity sake): entity darv_leaf_node i... Jaco Naude ltnaude.jaco@[EMAIL PROTECTED... Discussion 2008-11-25T23:52:04+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73795.html Footwear (paypal payment)(www.king-trade.cn ) Paul Smith shoes Jordan shoes Bape shoes Chanel shoes (paypal payment)(www.king-trade.cn ) DG shoes Dior shoes ED hardy shoes Evisu shoes Fendi shoes (paypal payment)(www.king-trade.cn ) Gucci shoes Hogan... 128 ltcheapbbc@[EMAIL PROTECTED] gt Discussion 2008-11-25T21:03:01+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73794.html shoes on AIR Jordan 1 (paypal payment)(www.king-trade.cn ) AIR Jordan 2 AIR Jordan 3 AIR Jordan 4 AIR Jordan 5 (paypal payment)(www.king-trade.cn ) AIR Jordan 6 Rings AIR Jordan 6 AIR Jordan 7 AIR Jordan 8 AIR Jordan 9 (paypal payment)(www.king-trad... 128 ltcheapbbc@[EMAIL PROTECTED] gt Discussion 2008-11-25T20:59:17+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73789.html hi all, 1) how does it matter for a cpld when i declare a constant or signal 2) what is the difference if i mention default value while declaration /without declaration 3) difference between below piece of tristate code output = a when enable= 1 els... sundar ltsundar.ece@[EMAIL PROTECTED] gt... Discussion 2008-11-25T04:17:00+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73784.html CALL FOR PAPERS and Call For Workshop/Session Proposals WORLDCOMP09 The 2009 World Congress in Computer Science, Computer Engineering, and Applied Computing ... A. M. G. Solo ltamgsolo@[EMAIL PROTECTED... Discussion 2008-11-23T21:17:03+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73778.html Hello, I have following error in line out1 = (others=0) BuffG.vhd : (47, 22): Keyword others is not allowed in unconstrained array aggregate. If out1 is constrained (out1: out STD_LOGIC_Vector(7 downto 0) everything work. How can I change below cod... MariuszK ltmariusz.kwiczala@[EMAIL PROTE... Discussion 2008-11-22T14:43:04+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73768.html Hi I am wondering if there is any way that I can write a std_logic_vector(31 downto 0) into a file and there is should be written then as a HEX value? Is there something like val = ABC(31 downto 0) write(s, hex(val)) Thanks Philipp ltPhilipp@[EMAIL PROTECTED] gt Discussion 2008-11-21T17:38:07+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73764.html Hi, Im a regular Quartus user who occasionally uses ISE to compile the same code. Just today I attempted to compile code that has been working in Quartus for several years now. However, Ive run into several compilation errors which have left me scra... Mark McDougall ltmarkm@[EMAIL PROTECTED]... Discussion 2008-11-21T11:20:17+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73760.html I think Ive broken my Modelsim. A couple of days ago things were working fine. Then I let XilinxUpdate bring me up to the latest models, and all of a sudden my directly instantiated components werent working. I told Modelsim to Refresh all of the ... Rob Gaddi ltrgaddi@[EMAIL PROTECTED] gt Discussion 2008-11-20T09:32:19+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73757.html I wrote a testbench in which i declared a variable ic as bit_vector (3 to 0). now when i tried putting ic:=ic + 1 inside a loop it shows operator argument type mismatch. I treid declaring it as signed and unsigned. whereismelvin@[EMAIL PROTECTED] Discussion 2008-11-20T00:20:47+00:00 http://www.talkaboutelectronicequipment.com/group/comp.lang.vhdl/messages/73746.html does anybody have a clear opinion about code generators ( c- vhdl , matlab- vhdl, etc..) that are around? Are they really irreplaceable in complex applications (i.e DSP) as the vendors say? abe lta.bergnoli@[EMAIL PROTECTED] gt Discussion 2008-11-19T07:47:00+00:00 Search talkaboutelectronicequipment.com VHDL q http://talkaboutelectronicequipment.com/group/comp.lang.vhdl/search.html