by Mike Treseler <mike_treseler@[EMAIL PROTECTED]
>
May 23, 2008 at 08:40 AM
Klaus Thiele wrote:
> The value is a decimal number
> between 0 and 15, so I wonder if VHDL offers an easy way to convert from
> decimal to binary so that I can compare then values with an AND mask.
> This the thing should also be sythesizable on an XIlinx FPGA ;)
I would declare that natural range as a subtype
and use a constant or variable of that subtype
for the comparison. Synthesis will work out
the details.
-- Mike Treseler
