On 26 May, 17:37, "HT-Lab" <han...@[EMAIL PROTECTED]
> wrote:
> <dejf...@[EMAIL PROTECTED]
> wrote in message
>
>
news:fa17637b-3631-4238-9b79-2061f475e3cb@[EMAIL PROTECTED]
>
>
>
> > Dear Experts,
> > i'd like to introduce to my design one register containing a firmware
> > revision. Very probably the firmware revision would be a data when the
> > VHDL code was checked out from the CVS repository where I store the
> > project.
>
> > The problem I encounter is how to translate the CVS last-commit data
> > of the project currently checked out, and translate it into VHDL code
> > to be a part of the project.
>
> > Example:
>
> > yesterday i committed at the end of day the whole project, thus when I
> > check it out today and burn, one of the registers I ex****t should
> > contain yesterday's date as a firmware revision
>
> > i check out the project corresponding to a date 2 weeks ago, the
> > firmware register should contain a number corresponding to date at
> > which the version of the project I have checked out was committed.
>
> > This would allow very easily match the firmware and CVS source
> > together.....
>
> > any ideas how to do it?
>
> > thanks
> > david
>
> Can't you use the $Id$/$Revision$ string in your source file and
translate
> that to a date/version constant with a bit of Tcl?
>
> This might help you a bit
:http://www.ht-lab.com/freeutils/date2hdl/date2hdl.html
>
> Hanswww.ht-lab.com
Hi,
Just out of interest, this is a solution that I implemented on a
previous project (i.e. based on CVS $Revision$ tag).
The problems I had with this
- It was based on the revision of a single file only rather than the
design as a whole. We therefore had to force revision updates of this
file when required (therefore we could have just used a VHDL
constant).
- It didn't handle "hacks". i.e. tem****ary RTL changes that were not
commited to CVS. Therefore we had different FPGA's
I would be interested to hear what mechanisms other people use on
bigger projects, and a non-ideal world ;-)
Steven
with different
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