Delta delay problem between multiple ****ts

I have Module1 with an output ****t ClkA.
Module1 is instantiated in Module2 that has the two output ****ts ClkA
and ClkB.


mapping Module1.ClkA to either module2.ClkA or Module2.ClkB without
delta delay is easy.

But, is there any VHDL constructs, such that:  Module1.ClkA can be
mapped to both Module2.ClkA and Module2.ClkB without any

delta delay difference  between these 3 ?

Thanks in advance
Trygve