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Re: VHDL switch model

by rickman <gnuarm@[EMAIL PROTECTED] > May 28, 2008 at 09:58 AM

On May 28, 10:25 am, Ralf Hildebrandt <Ralf-Hildebra...@[EMAIL PROTECTED]
> wrote:
> rickman schrieb:
>
> > I was considering what it will take to implement a bi-directional
> > switch in VHDL and found this by Peter Ashenden.  The method is pretty
> > much what I had thought of, but it does have one problem where a high
> > impedance on either side of the switch will not be conveyed to the
> > other once the bus has been set to a 1 or 0 state.  In essence, this
> > is not really a switch, but rather a bus keeper.
>
> Here is my solution:
>
<http://www.ralf-hildebrandt.de/publication/transfergate/transfergate.vhd>
>
<http://www.ralf-hildebrandt.de/publication/transfergate/tbench_transf...>
>
> Ralf

I had taken another look at Ben's code and found something I don't
understand.  I see the same thing in your code.  Maybe I have
forgotten something, but I thought a process had to either have a
sensitivity list, contain a loop or it would only be run once.  Both
your code and Ben's have no sensitivity list and no loop.  What am I
missing here?
 




 11 Posts in Topic:
VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-27 13:37:00 
Re: VHDL switch model
KJ <kkjennings@[EMAIL   2008-05-28 04:55:07 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 06:38:38 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 06:44:24 
Re: VHDL switch model
KJ <kkjennings@[EMAIL   2008-05-28 07:22:45 
Re: VHDL switch model
Ralf Hildebrandt <Ralf  2008-05-28 16:25:44 
Re: VHDL switch model
Rick <fmfoundry@[EMAIL  2008-05-31 18:25:01 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 09:58:29 
Re: VHDL switch model
"KJ" <kkjenn  2008-05-28 16:18:44 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 17:34:39 
Re: VHDL switch model
Ralf Hildebrandt <Ralf  2008-05-29 18:17:43 

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