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Re: VHDL switch model

by rickman <gnuarm@[EMAIL PROTECTED] > May 28, 2008 at 05:34 PM

On May 28, 4:18 pm, "KJ" <kkjenni...@[EMAIL PROTECTED]
> wrote:
> "rickman" <gnu...@[EMAIL PROTECTED]
> wrote in message
>
>
news:b0860289-99bb-4a45-a0cd-87e84935e868@[EMAIL PROTECTED]
>
> > On May 28, 10:25 am, Ralf Hildebrandt <Ralf-Hildebra...@[EMAIL PROTECTED]
> wrote:
> >> rickman schrieb:
>
> > I had taken another look at Ben's code and found something I don't
> > understand.  I see the same thing in your code.  Maybe I have
> > forgotten something, but I thought a process had to either have a
> > sensitivity list, contain a loop or it would only be run once.  Both
> > your code and Ben's have no sensitivity list and no loop.  What am I
> > missing here?
>
> A loop is not required.  A process must contain either a sensitivity
list or
> a wait statement.  All processes automatically 'restart' when they exit,
the
> only wait to have something run once is with an unconditional 'wait;' at
> some point.
>
> KJ

Is having this statement at the beginning of the process equivalent to
using a sensitivity list (without the "until" part)?

wait on wireA'transaction, wireB'transaction, sel'transaction until
last/=now;

I am not clear on the purpose of the "until" ****tion.  It looks to me
like it makes the process continue as soon as the "real" time
increments.  Is that right?  Having this run on every increment of
time seems pretty inefficient.

Does this "glitch" the bus on the delta cycles?  I mean will a
simulator display continuous transitions on these signals because of
the change from driving 'Z' vs. the other bus?

I need to fire up the simulator, but I don't have time right now.  But
then again, I need to use this, so maybe I don't have a choice.

Rick
 




 11 Posts in Topic:
VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-27 13:37:00 
Re: VHDL switch model
KJ <kkjennings@[EMAIL   2008-05-28 04:55:07 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 06:38:38 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 06:44:24 
Re: VHDL switch model
KJ <kkjennings@[EMAIL   2008-05-28 07:22:45 
Re: VHDL switch model
Ralf Hildebrandt <Ralf  2008-05-28 16:25:44 
Re: VHDL switch model
Rick <fmfoundry@[EMAIL  2008-05-31 18:25:01 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 09:58:29 
Re: VHDL switch model
"KJ" <kkjenn  2008-05-28 16:18:44 
Re: VHDL switch model
rickman <gnuarm@[EMAIL  2008-05-28 17:34:39 
Re: VHDL switch model
Ralf Hildebrandt <Ralf  2008-05-29 18:17:43 

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