****ft register extraction fails

Hi!

I'm trying to get Xilinx ISE 9.2 to synthesize a ****ft register for a
Spartan 3E. I'm down to copying this code:

entity ****ft is
  ****t(C, SI : in  std_logic;
        SO : out std_logic);
end ****ft;
architecture archi of ****ft is
  signal tmp: std_logic_vector(7 downto 0);
  begin
    process (C)
      begin
        if (C'event and C='1') then
          for i in 0 to 6 loop
            tmp(i+1) <= tmp(i);
          end loop;
          tmp(0) <= SI;
        end if;
    end process;
    SO <= tmp(7);
end archi;

from the xilinx website:
http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02007.htm

But still, ISE synthesizes D-Flipflops:
Synthesizing Unit <****ft>.
    Related source file is "...".
    Found 8-bit register for signal <tmp>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <****ft> synthesized.

And yes, ****ft register extraction and logical ****fter extraction in the
HDL options are checked.

Please, help me before I go mad...

-   Philip
-- 
Machen Sie sich erst einmal unbeliebt, dann werden
Sie auch ernst genommen. (Konrad Adenauer)