Re: ****ft register extraction fails

On Thu, 29 May 2008 10:21:53 +0200, Philip Herzog <phu@[EMAIL PROTECTED]
> wrote:

>Hi!
>
>I'm trying to get Xilinx ISE 9.2 to synthesize a ****ft register for a
>Spartan 3E. I'm down to copying this code:
>
>entity ****ft is
>  ****t(C, SI : in  std_logic;
>        SO : out std_logic);
>end ****ft;
>architecture archi of ****ft is
>  signal tmp: std_logic_vector(7 downto 0);
>  begin
>    process (C)
>      begin
>        if (C'event and C='1') then

Does the synthesiser recognise the preferred
	if rising_edge(C) then
instead?

- Brian