Re: VHDL switch model

rickman schrieb:

> Is having this statement at the beginning of the process equivalent to
> using a sensitivity list (without the "until" part)?

Without the until-part: yes.


> wait on wireA'transaction, wireB'transaction, sel'transaction until
> last/=now;
> 
> I am not clear on the purpose of the "until" ****tion.  It looks to me
> like it makes the process continue as soon as the "real" time
> increments.  Is that right?  Having this run on every increment of
> time seems pretty inefficient.

The process is stopped as long as the wait-condition is not met. Then it 
is run if last/=now. This makes simulation time acceptable.

I used this transfer gate to model an analog switch matrix outside of 
the ASIC for testbench purpose. The ASIC controls the switches and the 
testbench simulates the behavior of the other components on a PCB (the 
analog switches).

> Does this "glitch" the bus on the delta cycles?  I mean will a
> simulator display continuous transitions on these signals because of
> the change from driving 'Z' vs. the other bus?

Every time the transfer gate "fires" it generates a new event - even if 
the signal value does not change.


Ralf