On 30 Mai, 06:53, Thomas Stanka <usenet_nospam_va...@[EMAIL PROTECTED]
>
wrote:
> On 28 Mai, 16:21, Trygve Odegaard <tro...@[EMAIL PROTECTED]
> wrote:
>
> > I have Module1 with an output ****t ClkA.
> > Module1 is instantiated in Module2 that has the two output ****ts ClkA
> > and ClkB.
> > But, is there any VHDL constructs, such that: =A0Module1.ClkA can be
> > mapped to both Module2.ClkA and Module2.ClkB without any
>
> > delta delay difference =A0between these 3 ?
>
> Question: Why do you bother about delta delays?
> Use "Y <=3D X after 1 ns" for clocked signals and you have no problem
> with delta delays.
>
> There is no construct for signal assignment, that is free of delta
> delay, only variables are updated in the same tick, but I would'nt use
> variables for clocks, as i find it no good idea to have a rising edge
> of clock within one delta delay (would'nt suprise me, if the tools
> wouldn't sup****t this propperly).
>
> bye Thomas
My Module1 output data ( delta synchronously with clkA) in addition to
clkA. At he output of module2,
I still want both to be delta-synchronous, which is no problem. I
have already experienced how hard it is to debug HW-failures when the
simulation-OK is due to a architechually deeply buried delta offset.
The simple case with clock & data only, gives me no problem. The
problem arise when I want to take a clock, and split into two copies
at the next-higher level, still with all three copies at the same
delta.
Regards Trygve
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