moogyd@[EMAIL PROTECTED]
writes:
> I would be interested to hear what mechanisms other people use on
> bigger projects, and a non-ideal world ;-)
>
I embed the "time of compile" into the FPGA, using a TCL script to
create a (very simple) VHDL file.
I also overwrite that VHDL file after synthesis, so you can't
accidentally re-compile an FPGA with the same timestamp in it.
I also embed the timestamp into the UserID of the bitstream, which
means I can very easily read it out using JTAG, which is handy in some
cir***stances.
Cheers,
Martin
--
martin.j.thompson@[EMAIL PROTECTED]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
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