On 28 May, 15:21, Trygve Odegaard <tro...@[EMAIL PROTECTED]
> wrote:
> I have Module1 with an output ****t ClkA.
> Module1 is instantiated in Module2 that has the two output ****ts ClkA
> and ClkB.
>
> mapping Module1.ClkA to either module2.ClkA or Module2.ClkB without
> delta delay is easy.
>
> But, is there any VHDL constructs, such that: Module1.ClkA can be
> mapped to both Module2.ClkA and Module2.ClkB without any
>
> delta delay difference between these 3 ?
>
> Thanks in advance
> Trygve
There is no way to avoid adding delta delays with signal assignments.
SingalB <= SignalA will always add a 1 delta delay. Its unavoidable.
I still dont understand why you are so worried. Delta delays are
infinitely small, so have no meaning in reality. If you are having
problems with variables updating, then I suggest that you are
triggering a process in the wrong way.
To align deltas in processes, you can add 1 delta wait states:
wait for 0 ns; will hold a process for 1 delta.
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