Re: String to std_logic_vector

On May 30, 12:16=A0pm, Shannon <sgo...@[EMAIL PROTECTED]
> wrote:
> I've been searching here but all the hits were for converting SLV to
> string for testbenches.
>
> I'm looking to convert a string to an array of 8bit SLVs. =A0The idea is
> I have a revision string of fixed length- something like:
>
> ver <=3D "005-0805300908x2"'
>
> and I have an array of registers declared as such:
>
> SUBTYPE hwid_type is STD_LOGIC_VECTOR(7 DOWNTO 0);
> TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type;
> SIGNAL =A0regs : reg_type;
>
> What I'm looking for is a loop shown here in psuedo code:
>
> for i in 1 to 16 loop
> =A0 =A0 regs(i) <=3D to_slv(ver(mid$(i,1)))
> end loop
>
> Note this is for synthesis so I don't know if any of this is even
> legal. =A0I am trying to create a version register that the
> microprocessor can read. =A0An ascii string is prefered - let's pretend
> for a moment it is a requirement. =A0This is also a learning exercise
> for me to deal with strings in VHDL.
>
> Any ideas?
>
> Shannon

Since your input string has some non-numeric characters in it that you
presumably want to keep in the string, then the best approach would be
to simply write a function that parses the string however you'd like.

Below is an example that simply adds the 'value' of each input
character to produce an integer output.  You should be able to easily
modify this to select out whichever characters you want and perform
whatever calculations you'd like.

function Version_String_To_integer(Some_String: STRING) return integer
is
variable Return_Value: integer :=3D 0;
begin
for i in Some_String'range loop
  Some_Char :=3D Some_String(i)
  case Some_Char is
     when "0" =3D> Return_Value :=3D Return_Value + 0;
     when "1" =3D> Return_Value :=3D Return_Value + 1;
     ...
     when others =3D> null;
  end case;
end loop;
return(Return_Value);
end function Version_String_To_integer;

KJ