Re: ****ft register extraction fails

Philip Herzog wrote:
> Hi!
> 
> I'm trying to get Xilinx ISE 9.2 to synthesize a ****ft register for a
> Spartan 3E. I'm down to copying this code:
> 
> entity ****ft is
>   ****t(C, SI : in  std_logic;
>         SO : out std_logic);
> end ****ft;
> architecture archi of ****ft is
>   signal tmp: std_logic_vector(7 downto 0);
>   begin
>     process (C)
>       begin
>         if (C'event and C='1') then
>           for i in 0 to 6 loop
>             tmp(i+1) <= tmp(i);
>           end loop;
>           tmp(0) <= SI;
>         end if;
>     end process;
>     SO <= tmp(7);
> end archi;
> 
> from the xilinx website:
> http://toolbox.xilinx.com/docsan/3_1i/data/fise/xst/chap02/xst02007.htm
> 
> But still, ISE synthesizes D-Flipflops:
> Synthesizing Unit <****ft>.
>     Related source file is "...".
>     Found 8-bit register for signal <tmp>.
>     Summary:
> 	inferred   8 D-type flip-flop(s).
> Unit <****ft> synthesized.
> 
> And yes, ****ft register extraction and logical ****fter extraction in the
> HDL options are checked.
> 
> Please, help me before I go mad...
> 
> -   Philip

Philip:
I put this code in ISE 10.1 and got the same message.  However, the 
message is erroneous or ambiguous and the synthesizer is actually using 
an SRL.  The design is actually implemented using one SRL (with a delay 
of 5) and an input and output flop (to improve timing, since the i/o 
connect to pins).

Look at the technology schematic to prove this.  Also, if you look at 
the utilization re****t section of the XST log file, you should see this:

Slice Logic Utilization:
  Number of Slice Registers:               2  out of  19200     0%
  Number of Slice LUTs:                    1  out of  19200     0%
     Number used as Memory:                1  out of   5120     0%
        Number used as SRL:                1

I have found that you can sometimes use better style than the templates 
in the XST user's guide and they still synthesize properly.  This code, 
which I think is better style, synthesizes the same way:

library ieee;
use ieee.std_logic_1164.all;
entity ****ft_registers_1 is
   ****t(C, SI : in std_logic;
        SO : out std_logic);
end ****ft_registers_1;
architecture archi of ****ft_registers_1 is
   signal SI_dly : std_logic_vector(7 downto 0);
begin
   process (C)
   begin
     if (rising_edge(C)) then
       SI_dly <= SI_dly(6 downto 0) & SI;
     end if;
   end process;
   SO <= SI_dly(7);
end archi;

-Kevin