Re: ****ft register extraction fails

Kevin Neilson wrote:
> I have found that you can sometimes use better style than the
> templates in the XST user's guide and they still synthesize properly.
> This code, which I think is better style, synthesizes the same way:

> library ieee;
> use ieee.std_logic_1164.all;
> entity ****ft_registers_1 is
>   ****t(C, SI : in std_logic;
>        SO : out std_logic);
> end ****ft_registers_1;
> architecture archi of ****ft_registers_1 is
>   signal SI_dly : std_logic_vector(7 downto 0);
> begin
>   process (C)
>   begin
>     if (rising_edge(C)) then
>       SI_dly <= SI_dly(6 downto 0) & SI;
>     end if;
>   end process;
>   SO <= SI_dly(7);
> end archi; 

I like this style even better, since you only have to change one single
line of code (the signal declaration) when you want to change the delay
later on:

library ieee;
use ieee.std_logic_1164.all;
entity ****ft_registers_1 is
  ****t(C, SI : in std_logic;
       SO : out std_logic);
end ****ft_registers_1;
architecture archi of ****ft_registers_1 is
  signal SI_dly : std_logic_vector(7 downto 0);
begin
  process (C)
  begin
    if (rising_edge(C)) then
      SI_dly <= SI_dly(SI_dly'length-2 downto 0) & SI;
    end if;
  end process;
  SO <= SI_dly(SI_dly'left);
end archi;

This also works if you later decide to pass the length of SI_dly as a
GENERIC when instantiating the thing.

cu,
Sean