Two processes with communication through a signal.

signal trigger;

proc1 : process(clk)
begin
trigger <= '0';
case state_proc1 is
  when ... (other states)
  when STATE1 =>
    trigger <= '1';
    state_proc1 <= STATE2;
  when STATE2 =>
    -- do something, but don't set trigger to anything
  when ... (other states)
end case;
end process proc1;

proc2 : process(clk)
begin
case state_proc2 is
  when STATE1 =>
    if trigger = '1' then
      state_proc2 <= STATE2;
    end if;
  when STATE2 =>
    -- do something
    state_proc2 <= STATE1;
end case;
end process proc2;

Can proc1 transition from (some state)->STATE1->STATE2->(some other
state) without causing proc2 to transition from STATE1 to STATE2?
(assuming state_proc2 is STATE1 to start)

I have similar code which is implemented on a FPGA where proc2 somehow
misses the trigger signal going high unless I keep it high for a few
clock cycles and I really don't understand how this can happen.  I
thought in the above case both processes would run and then pending
signal assignments (such as trigger going to 1) would be made
simultaneously after a delta delay.

If this is indeed not possible, any ideas on trying to identify what
is causing this?

Thanks!