Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Sat, 31 May 2008 11:58:04 -0700 (PDT), nitrogenocide wrote:

>After running "check syntax", I get the following errors.

>ERROR:HDLParsers:3292 - "D:/PFiles/SS08/SS08.vhd" Line 92. = has two
>or more possible definitions in this scope.  For example, parameter 2
>(string value) can be: SIGNED or UNSIGNED
[etc]
>Line 92:    if setup_sample = "1111111" then
[etc]

>The errors seem to be implying that I haven't specified these signals
>as either signed or unsigned.  But the following part of my code does
>specify all these signals as unsigned

Intriguingly, this exact issue came up here only a couple 
of days ago.

It's almost certainly because you are accepting the goofy 
Xilinx default VHDL code template which has, inter alia,

  USE IEEE.STD_LOGIC_ARITH.all;

No-one can explain why Xilinx (and others too) continue
to recommend in this way the use of a package that was
superseded by the better, more complete, properly
standardised IEEE.NUMERIC_STD over a decade ago.

The specific issue is that STD_LOGIC_ARITH provides
definitions of the "=" operator for all the following
combinations of types:

  UNSIGNED = UNSIGNED
  UNSIGNED = SIGNED
    SIGNED = UNSIGNED
    SIGNED = SIGNED

If the things on the opposite sides of the "=" are
simple variables or signals, that's fine - but if they
are expressions, or literals like your "111111", there
is a type ambiguity because the literal might be either
SIGNED or UNSIGNED, and VHDL can't work out which it is.

The preferred fix is to replace STD_LOGIC_ARITH with
NUMERIC_STD.  This will fix the type ambiguity issue, but
it may give you a few other compile errors because the
conversion functions' names have changed: conv_integer()
is now to_integer, and conv_unsigned() is now called 
to_unsigned().  Obviously, those will be rather easy
to deal with.  This is by far the most satisfactory
solution.  NUMERIC_STD defines equality for
UNSIGNED=UNSIGNED and for SIGNED=SIGNED, but not
for combinations of the two - so, in your comparison,
there is only one possible interpretation of the 
constant and VHDL will get it right automatically.

The less satisfactory fix (hack) is to make the type
of your constants explicit:

  if setup_sample = UNSIGNED'("1111111") then

This is known as a "type qualification"; note the
apostrophe between the type name and the opening
parenthesis.

I have no idea why this didn't throw an error in ISE9.1.
-- 
Jonathan Bromley, Consultant

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