Re: Signed, Unsigned syntax issues. Please help, I'm stumped

"Jonathan Bromley" <jonathan.bromley@[EMAIL PROTECTED]
> wrote in message 
news:q0a344h9akcforb27c31h38tre70d2oaml@[EMAIL PROTECTED]
> On Sat, 31 May 2008 11:58:04 -0700 (PDT), nitrogenocide wrote:
>
>
> Intriguingly, this exact issue came up here only a couple
> of days ago.
>

A regular conspiracy going on ;)

> It's almost certainly because you are accepting the goofy
> Xilinx default VHDL code template which has, inter alia,
>
>  USE IEEE.STD_LOGIC_ARITH.all;
>
> No-one can explain why Xilinx (and others too) continue
> to recommend in this way the use of a package that was
> superseded by the better, more complete, properly
> standardised IEEE.NUMERIC_STD over a decade ago.
>

That would bring them up to the 90s now wouldn't it....only 15 or so years

behind the standards.

>
> The less satisfactory fix (hack) is to make the type
> of your constants explicit:
>
>  if setup_sample = UNSIGNED'("1111111") then
>
> This is known as a "type qualification"; note the
> apostrophe between the type name and the opening
> parenthesis.
>

If for some reason you reeeeeally didn't want to properly define a
constant 
to do the job, I think using the type qualifier is better (not a hack) 
since, even if the compiler has no ambiguity, the reader may and having
the 
type qualifier makes it explicit to the reader as to the intended 
type...do***entation comes in all forms.

Kevin Jennings