by KJ <kkjennings@[EMAIL PROTECTED]
>
Jun 2, 2008 at 01:12 PM
On Jun 2, 4:10=A0pm, FP <FPGA.unkn...@[EMAIL PROTECTED]
> wrote:
> How do I design a clock divider without using initial conditions.
With a reset signal.
> I designed once using initial values but they dont mean anything in
> synthesis.
>
If your targetted part has a specified power up state and the tools
that you choose to use sup****t initial values then initial values will
work just fine.
KJ
