Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On May 31, 4:53 pm, "KJ" <kkjenni...@[EMAIL PROTECTED]
> wrote:
> "Jonathan Bromley" <jonathan.brom...@[EMAIL PROTECTED]
> wrote in message
>
> news:q0a344h9akcforb27c31h38tre70d2oaml@[EMAIL PROTECTED]
>
> > On Sat, 31 May 2008 11:58:04 -0700 (PDT), nitrogenocide wrote:
>
> > Intriguingly, this exact issue came up here only a couple
> > of days ago.
>
> A regular conspiracy going on ;)
>
> > It's almost certainly because you are accepting the goofy
> > Xilinx default VHDL code template which has, inter alia,
>
> >  USE IEEE.STD_LOGIC_ARITH.all;
>
> > No-one can explain why Xilinx (and others too) continue
> > to recommend in this way the use of a package that was
> > superseded by the better, more complete, properly
> > standardised IEEE.NUMERIC_STD over a decade ago.
>
> That would bring them up to the 90s now wouldn't it....only 15 or so
years
> behind the standards.

I opened up a Web Case about this. Let's see if they give a ****.

Oh, yeah, in that same Web Case, I suggested that their templates use:

   if rising_edge(clk) then

instead of

   if (clk'event and clk = '1') then

It's almost halfway through 2008 ...

=-a