I am using a subtype to define a range as used in a SLV declaration.
subtype INST_RNG is natural range 23 downto 0;
signal CTPCurCmd : std_logic_vector (INST_RNG);
But if I try to use the same subtype to define a sub-range in an
assignment, I get this error message.
# Error: COMP96_0263: IRIG_FPGA_TB.vhd : (504, 68): Type names are not
allowed as primaries.
Is this just a limitation of the tool I am using or is this a language
issue? Is there a better way to define ranges so the parts of an
array can be dealt with symbolically?
Rick
