I am using the Lattice tools which include the Active HDL simulator.
I understand a lot of things about VHDL and FPGAs and all sorts of
electronics. But I can stumble over very trivial things in a tool.
Right now I have a project set up and have simulated it and produced
bit files which load into the device and run (more or less). But it
seems that every time I exit the simulator and re-enter, it forgets
where the source files are. When I add files to a project it seems to
want to make a copy in the ../work/src directory. Then any changes I
make to the originals have to be copied to this directory. Obviously
this is a PITA.
I figured out that I can use the original location for the files by
unselecting a check box that says (make local copy). If I do that and
re-open the tool, it shows no source files. It seems to be looking in
the ../work/src directory.
Does anyone out there use the Lattice tools with Active HDL? This is
the $900 version of ispLever and the simulator is the version that
comes with the Lattice package.
I was getting some good sup****t from an FAE, but I haven't heard from
him in a day or so and I need to figure this out.
I really get tired of fighting the tools. I much prefer to get work
done.
Rick
