On Sat, 7 Jun 2008 12:17:08 -0700 (PDT), HansWernerMarschke@[EMAIL PROTECTED]
>type array_of_std_logic_vector is array (0 to
>number_of_rotors_array-1) of std_logic_vector(0 to
>data_width_array-1);
>signal data_out_array : array_of_std_logic_vector;
>
>I want to "or" the "bits" of std_logic_vector for each element of the
>vector like this.
>data_out(i) shall be '1' if one of the elements of the vector has set
>this bit to one.
>
>data_out(0) <= '1' when unsigned(data_out_array(0)) /= 0;
>data_out(1) <= '1' when unsigned(data_out_array(1)) /= 0;
>
>The problem is that number_of_rotors and although data_width_array are
>generic.
That's not so much a problem as a solution waiting to happen...
for i in data_out_array'range loop
data_out(i) <= reduction_or(data_out_array(i));
end loop;
Oh, the function...
function reduction_or(v: in std_logic_vector) return std_logic is
variable r_or: std_logic;
begin
r_or := '0';
for i in v'range loop
r_or := r_or or v(i);
end loop;
return r;
end;
This is the sort of thing that VHDL does best.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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jonathan.bromley@[EMAIL PROTECTED]
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