Re: Signed, Unsigned syntax issues. Please help, I'm stumped

rickman
> I have seen to_unsigned(), unsigned() and unsigned'.  I understand
> that the first to are conversion and type casting respectively.  What
> is the third called?  I expect this is only for use where a literal or
> expression can be interpreted more than one way and explains to the
> tool what is intended, right?
See:
http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Or if you don't like going directly to pdf, go to:
http://www.synthworks.com/papers/

and select the paper, "VHDL Math Tricks of the Trade" from the
conference, MAPLD 2003.

Best,
Jim
SynthWorks VHDL Training