Re: Signed, Unsigned syntax issues. Please help, I'm stumped

rickman wrote:

> I have seen to_unsigned(), unsigned() and unsigned'.  I understand
> that the first to are conversion and type casting respectively.  What
> is the third called?  I expect this is only for use where a literal or
> expression can be interpreted more than one way and explains to the
> tool what is intended, right?

  That's it.

> I read back a bit and see that it is a "type qualification".  I think
> I got all that now.  So even when types are closely related, you still
> have to explicitly tell the tool to change the interpretation.

Yes, but keep in mind that I don't need *any* of these
functions if I declare my variable and constant
vectors correctly in the first place.
Here's an example of how I do this using subtypes:
 http://mysite.verizon.net/miketreseler/sync_template.vhd

And don't leave home without your cheat sheets:
 http://www.vhdl.org/rassp/vhdl/guidelines/vhdlqrc.pdf
 http://www.vhdl.org/rassp/vhdl/guidelines/1164qrc.pdf

> I think I wish I had started with Verilog instead of VHDL.  At least
> now if I start coding in Verilog, it will be an informed decision.

I expect that it would take longer
to learn verilog well than to learn
the vhdl numeric libraries.
If Andy were here, he would remind you
that integer ranges also work fine for synthesis
and require no libraries.

> The little Verilog I have coded was very easy to do and I did it with
> *no* additional training.  I just picked up a little from a book and
> the rest came pretty easy.

It's a rose for easy projects, but just thorns for debugging
complicated modules with signed and unsigned math.

> Does Verilog sup****t user libraries in a similar manner to VHDL?

No.


        -- Mike Treseler