Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Jun 10, 5:59 pm, Andy <jonesa...@[EMAIL PROTECTED]
> wrote:
> On Jun 9, 6:55 pm, rickman <gnu...@[EMAIL PROTECTED]
> wrote:
>
>
>
> > On Jun 9, 2:28 pm, Mike Treseler <mike_trese...@[EMAIL PROTECTED]
> wrote:
>
> > > rickman wrote:
> > > > ---No matching overload for "/="---
>
> > > > DataOutReg is slv and CTPCurCmd is unsigned.  I thought that the
two
> > > > types were "closely related" which means I don't have to use
> > > > conversions to intermix them.
>
> > > No, closely related means I can use
> > > a cast instead of a conversion as in:
>
> > >  unsigned(DataOutReg) /= CTPCurCmd(DAT_RNG)
>
> > > Let's look up the "/=" functions available
> > > in the numeric_std source here:
>
> > >http://www.cs.umbc.edu/help/VHDL/packages/numeric_std.vhd
>
> > >   function "/=" (L,R: UNSIGNED )            return BOOLEAN;
> > >   function "/=" ( L,R: SIGNED)              return BOOLEAN;
> > >   function "/=" ( L: NATURAL;  R: UNSIGNED) return BOOLEAN;
> > >   function "/=" ( L: INTEGER;  R: SIGNED)   return BOOLEAN;
> > >   function "/=" ( L: UNSIGNED; R: NATURAL)  return BOOLEAN;
> > >   function "/=" ( L: SIGNED;   R: INTEGER)  return BOOLEAN;
>
> > > For your example, a cast is needed to match the first signature.
>
> > >          -- Mike Treseler
>
> > I have seen to_unsigned(), unsigned() and unsigned'.  I understand
> > that the first to are conversion and type casting respectively.  What
> > is the third called?  I expect this is only for use where a literal or
> > expression can be interpreted more than one way and explains to the
> > tool what is intended, right?
>
> > I read back a bit and see that it is a "type qualification".  I think
> > I got all that now.  So even when types are closely related, you still
> > have to explicitly tell the tool to change the interpretation.
>
> > I think I wish I had started with Verilog instead of VHDL.  At least
> > now if I start coding in Verilog, it will be an informed decision.
> > The little Verilog I have coded was very easy to do and I did it with
> > *no* additional training.  I just picked up a little from a book and
> > the rest came pretty easy.
>
> > Does Verilog sup****t user libraries in a similar manner to VHDL?
>
> > Rick
>
> A long time ago there was a live design/coding contest between being
> Verilog and VHDL to code a small module that had a few strange
> requirements, but was otherwise pretty straight forward. Verilog
> trounced VHDL. But if you stopped there, and assumed Verilog was
> better than VHDL for most digital design, you missed the point.
> Anything that can be converted from spec to synthesized gates in an
> hour or two will almost necessarily be the easiest/quickest to design
> in the simplest, most constrained language capable of doing that
> simple job, namely verilog. Is that the basis upon which you want to
> choose your development language?

I recall that competition and I seem to recall that it was *very*
inconclusive.  Although the Verilog teams seemed to be further along,
not one team produced working code in the time alloted.  I guess this
could be a different contest though.


> To keep Mike an honest man: VHDL synthesis tools sup****t arithmetic
> for integers without additional libraries. However, bit-wise logic
> operations on integers are not sup****ted without custom libraries, and
> standard ranges for integers limit data widths to 31 bits unsigned and
> 32 bit signed.

I don't care if libraries are required for various features.  I was
asking about sup****t for user libraries in Verilog.  I believe the
answer was no.  Is that still valid?


> One more point: just try to design a fixed or floating point
> arithmetic design with verilog!

Is that a point?  What was the point?  Are you trying to say that
users don't design arithmetic circuits in Verilog??? I am pretty sure
that the limited work I have done in Verilog has included arithmetic.
I must be missing your point.


BTW, here is one of the reasons I am getting tried of using VHDL.  I
have coded FPGAs in VHDL off and on for some 10 years.  Every time I
start a new design (sometimes as long as 18 months since the last one)
I have to pick up all of my books again to remember the details and to
read my notes on the various shortcuts to efficient use.  I typically
find that the shortcuts are not very short and look for new ones.  The
notation is just so verbose for simple things.  Here is an example.

CTPBitCnt is an unsigned.

What I mean...
  CTPBitCnt <= 1;

What I have to write...
  CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);

Doesn't that seem a bit wordy?  I guess this example goes back to the
inability to overload the assignment operator which someone has
indicated may be changed in the next revision of the language.

Rick