Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Jun 11, 11:52=A0am, rickman <gnu...@[EMAIL PROTECTED]
> wrote:
> On Jun 10, 5:59 pm, Andy <jonesa...@[EMAIL PROTECTED]
> wrote:
> notation is just so verbose for simple things. =A0Here is an example.
>
> CTPBitCnt is an unsigned.
>
> What I mean...
> =A0 CTPBitCnt <=3D 1;
>
> What I have to write...
> =A0 CTPBitCnt <=3D to_unsigned(1, CTPBitCnt'length);
>
> Doesn't that seem a bit wordy? =A0I guess this example goes back to the
> inability to overload the assignment operator which someone has
> indicated may be changed in the next revision of the language.
>

I agree it is too wordy and also prone to error (like if you get
sloppy and type "8" instead of "CTPBitCnt'length" and then later
change the range of "CTPBitCnt")

If this were legal...

CTPBitCnt <=3D to_unsigned(1)

I wouldn't think it to be too wordy since it is specifying a type
conversion and having explicit type conversions is preferrable (to
me).

In the meantime one could create a procedure like the following and
put it into a package of commonly used VHDL shortcuts...

procedure set(L: out unsigned; R: in integer) is
begin
  L :=3D to_unsigned(R, L'length);
end procedure set;

which could then be used like this...
set(Test_Set, 1);

But then you'd need to overload it so you could pass signals instead
of variables...and hope that the name 'set' (or whatever you come up
with) sticks in your mind as to be clear about what it's purpose
is....sigh

Kevin Jennings