Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Jun 11, 2:41 pm, KJ <kkjenni...@[EMAIL PROTECTED]
> wrote:
> On Jun 11, 2:14 pm, Mike Treseler <mike_trese...@[EMAIL PROTECTED]
> wrote:
>
> > rickman wrote:
> > > What I mean...
> > >   CTPBitCnt <= 1;
>
> > > What I have to write...
> > >   CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);
>
> > > Doesn't that seem a bit wordy?
>
> > Yes. Declare CTPBitCnt unsigned instead of std_logic_vector.
>
> He did declare it as unsigned.
>
> >     CTPBitCnt <=  x"0001";

This works with signed, unsigned and SLV!

> Doesn't work though if the length of CTPBitCnt is anything other than
> a multiple of 4 bits (i.e. CTPBitCnt: unsigned(12 downto 0));

Worse, I have to hard code the width of the signal which I try to
avoid.  That is why I want to assign it a value from an integer and
not specify every bit in the vector.  For example, all of my address
values are currently 8 bits.  My customer may decide to change the
protocol to use 6 bits since that is plenty enough.  I would hate to
have to go through the entire body of code changing 8 bit constants to
6 bits.

VHDL just makes life hard in some ways.

Rick