Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Jun 11, 12:17=A0pm, KJ <kkjenni...@[EMAIL PROTECTED]
> wrote:
> On Jun 11, 11:52=A0am, rickman <gnu...@[EMAIL PROTECTED]
> wrote:

>
> In the meantime one could create a procedure like the following and
> put it into a package of commonly used VHDL shortcuts...
>
> procedure set(L: out unsigned; R: in integer) is
> begin
> =A0 L :=3D to_unsigned(R, L'length);
> end procedure set;
>
> which could then be used like this...
> set(Test_Set, 1);
>
> But then you'd need to overload it so you could pass signals instead
> of variables...and hope that the name 'set' (or whatever you come up
> with) sticks in your mind as to be clear about what it's purpose
> is....sigh
>

Slight correction to the previous.  You can't overload the 'set'
function to have one that works with signals and another that works
with variables, you'd need to have two distinctly named functions
(i.e. 'setsig' and 'setvar')...all for the lack of being able to
overload the assignment operators....

KJ