Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Wed, 11 Jun 2008 08:52:56 -0700 (PDT), rickman <gnuarm@[EMAIL PROTECTED]
>
wrote:

>BTW, here is one of the reasons I am getting tried of using VHDL.  I
>have coded FPGAs in VHDL off and on for some 10 years.  Every time I
>start a new design (sometimes as long as 18 months since the last one)
>I have to pick up all of my books again to remember the details and to
>read my notes on the various shortcuts to efficient use.  I typically
>find that the shortcuts are not very short and look for new ones.  The
>notation is just so verbose for simple things.  Here is an example.
>
>CTPBitCnt is an unsigned.
>
>What I mean...
>  CTPBitCnt <= 1;
>
>What I have to write...
>  CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);
>
>Doesn't that seem a bit wordy?  I guess this example goes back to the
>inability to overload the assignment operator which someone has
>indicated may be changed in the next revision of the language.


Ironically, thanks to overloaded operators,

CTPBitCnt <= (others => '0') + 1;

will work, and I would hope any synthesis tool would realise both inputs
are constant.

It's not pretty though...

- Brian