Re: Signed, Unsigned syntax issues. Please help, I'm stumped

rickman
> BTW, here is one of the reasons I am getting tried of using VHDL.  I
> have coded FPGAs in VHDL off and on for some 10 years.  Every time I
> start a new design (sometimes as long as 18 months since the last one)
> I have to pick up all of my books again to remember the details and to
> read my notes on the various shortcuts to efficient use.  I typically
> find that the shortcuts are not very short and look for new ones.  The
> notation is just so verbose for simple things.  Here is an example.
> 
> CTPBitCnt is an unsigned.
> 
> What I mean...
>   CTPBitCnt <= 1;
> 
> What I have to write...
>   CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);
> 
> Doesn't that seem a bit wordy?  I guess this example goes back to the
> inability to overload the assignment operator which someone has
> indicated may be changed in the next revision of the language.

Jonathan just submitted a language feature request WRT to overloading
assignment, however, the standard is already at the balloting point so
it will not make the 2008 revision.

What has been added is a decimal notation for bit string literals
and a sizing indication.

signal CTPBitCnt : unsigned (14 downto 0) ; -- 15 bits
.. . .
-- Representing 1 as a 15 bit object in either hex or decimal

CTPBitCnt <= 15D"1" ;   -- Decimal notation
CTPBitCnt <= 15X"1" ;   -- Hex notation

BTW, these are also in Accellera standard VHDL-2006-rev3.0, so
if your vendors were looking out for your interests, they would
have already should implemented these.

Make sure to submit these as bug/enhancement requests.  This is im****tant
as this is what lets them know the VHDL community wants the new features.

Best,
Jim

P.S.  Did you grab the paper I referenced:
   http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf