Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Jun 12, 2:42 pm, Jim Lewis <j...@[EMAIL PROTECTED]
> wrote:
> rickman
>
>
>
> > BTW, here is one of the reasons I am getting tried of using VHDL.  I
> > have coded FPGAs in VHDL off and on for some 10 years.  Every time I
> > start a new design (sometimes as long as 18 months since the last one)
> > I have to pick up all of my books again to remember the details and to
> > read my notes on the various shortcuts to efficient use.  I typically
> > find that the shortcuts are not very short and look for new ones.  The
> > notation is just so verbose for simple things.  Here is an example.
>
> > CTPBitCnt is an unsigned.
>
> > What I mean...
> >   CTPBitCnt <= 1;
>
> > What I have to write...
> >   CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);
>
> > Doesn't that seem a bit wordy?  I guess this example goes back to the
> > inability to overload the assignment operator which someone has
> > indicated may be changed in the next revision of the language.
>
> Jonathan just submitted a language feature request WRT to overloading
> assignment, however, the standard is already at the balloting point so
> it will not make the 2008 revision.
>
> What has been added is a decimal notation for bit string literals
> and a sizing indication.
>
> signal CTPBitCnt : unsigned (14 downto 0) ; -- 15 bits
> . . .
> -- Representing 1 as a 15 bit object in either hex or decimal
>
> CTPBitCnt <= 15D"1" ;   -- Decimal notation
> CTPBitCnt <= 15X"1" ;   -- Hex notation
>
> BTW, these are also in Accellera standard VHDL-2006-rev3.0, so
> if your vendors were looking out for your interests, they would
> have already should implemented these.
>
> Make sure to submit these as bug/enhancement requests.  This is
im****tant
> as this is what lets them know the VHDL community wants the new
features.
>
> Best,
> Jim
>
> P.S.  Did you grab the paper I referenced:
>    http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Yes, I looked at it.  I especially like the comment at the bottom of
page 5

"Some think VHDL is difficult because of strong typing
Master the above simple rules and it is easy"

No, it is not "easy".  It is ***bersome and crude.  Strong typing is
not the problem, verbosity is!  Strong typing may keep you from
screwing up certain things that novices might do, but VHDL is a clumsy
language.  Just as you point out above, there are any number of ways
to make the language more succinct and readable, not to mention
helping to let my tendinitis heal.  It is hard to imagine that it has
taken over 20 years for many of these simple ideas to be
implemented.

Maybe I am being overly critical.  Right now I am pretty ticked off
about the Lattice/Aldec tools I paid a kilobuck for.  It won't even
let me make a test bench out of the file I wrote for another chip.

I have a mind to abandon VHDL so that I can use the open source
Verilog tools.  It may be too late to use them on this design, but I
will look very hard at open source before I start my next design.

Rick