I have designed a unit that I am testing in modelsim. I did that in
two ways, first forcing the inputs from the object pull down menu of
the vsim window and clicking on the run command and second by writing
a test bench. However, I find that in the first case the inputs need
to arrive two clock pulses after the reset goes high as is also true
logically in my design whereas in the test bench, the outputs get the
correct values if the input enters one clock pulse after the reset
goes high else if it enters two clock pulses after the reset goes high
as in the first case then the last data sample is not written and the
output takes on the previous value. If I try to input data one clock
pulse after reset goes high in the first case as in the second case
then the last sample overwrites the previous last before the previous
last is out, which is also true logically.What is the problem with the
test bench?
This is a part of the test bench that reads the data depending on the
reset2 signal that has to be set high after one clock pulse, the reset
goes high else that causes problem as mentioned above. This is just a
signal I have used to control reading operation in the test bench.
readfile :PROCESS
file inp1:TEXT open READ_MODE is "inp1.txt";
file inp2:TEXT open READ_MODE is "inp2.txt";
VARIABLE inline1,inline2 : LINE;
variable dat_var : std_logic_vector (11 DownTo 0);
variable add_var : std_logic_vector (2 DownTo 0);
BEGIN
WAIT UNTIL (clock1 = '1' AND clock1'EVENT);
IF (NOT ENDFILE(inp1)) and reset2 = '1' then -----reading data
READLINE(inp1, inline1);
READ(inline1, dat_var);
datain1 <= dat_var;
count_read <= count_read+1;
END IF;
IF (NOT ENDFILE(inp2)) and reset2 = '1' THEN --------reading address
READLINE(inp2, inline2);
READ(inline2, add_var);
write_add <= add_var;
count_read <= count_read+1;
END IF;
end process readfile;
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