Re: Signed, Unsigned syntax issues. Please help, I'm stumped

KJ,
> A: CTPBitCnt <= 1;
> B: CTPBitCnt <= to_unsigned(1);
> C: CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);
> D: set(CTPBitCnt, "<=", 1);
> E: CTPBitCnt <= 15D"1"
> F: CTPBitCnt <= CTPBitCnt'length D"1";??

A couple of comments.
Which of these solutions work for numbers larger than 31 bits?

Beyond strong typing, I think the array sizing rules are im****tant.
Tensilica presented a paper at DVCon some years back where they
imposed lint rules on their Verilog coders to facilitate the translation
to VHDL.  These lint rules enforced the array sizing rules in numeric_std.
The number I remember was that when the lint rule fired off, 75% of the
time it was an error.  Anyone hear (or from Tensilica know) a different
number?


 > 'E' is valid VHDL'2008 that has lost the designer's intent...15B??
 > hmmm....
 >
 > 'F' might be valid VHDL'2008, not sure.  But in order to write code
 > that you don't have to keep re-writing when the width of 'CTPBitCnt'
 > changes is how you would want to express it.  Even if it were legal,
 > it is just a butt ugly version of what is currently available with
 > VHDL'93.  It's not an improvement, it's worse.  Not only do you have
 > to specify the width (as you do today) but now the intent of the
 > statement is only clear to those who understand that a 'D' or an 'X'
 > preceding a constant is specifying the bit width of the
 > constant....ummmm....OK, I think I'll stick with today's to_unsigned
 > notation.

For details about signed, unsigned, meaning of D or X, see my
presentations.
Since I have been posting links to the presentation, I am surprised you
waited to reflect such negative comments.

If you want to have an opinion in what is done, I suggest that you
PARTICIPATE in the standards.

Cheers,
Jim Lewis
SynthWorks
IEEE VHDL and Analysis Standards Group, http://www.eda.org/vasg