Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Sun, 15 Jun 2008 10:32:43 -0700, Jim Lewis wrote:

>> [overloaded := operator] would prevent errors that are 
>> currently unavoidable: if you use := or <= to copy a 
>> fixed-point value from one place to another, and the 
>> target object is of the wrong subytpe, you can get its
>> fixed-point scaling silently and disastrously screwed-up.
>
>For fixed point math, to address the range issue, this seems
>reasonable, but it also seems open other issues.  For example,
>if I use an intermediate object that is too small, overloading
>":=" will automatically downsize it.

This is true, although errors of precision seem to me
to be less disastrous than errors of scaling.  In truth,
there is probably no one-size-fits-all solution to this
kind of problem.  For example, fixed-point math surely
needs both saturating and truncating forms of overflow;
how can that be controlled, for individual assignments, 
without needing very clunky syntax?

VHDL is a million miles ahead of Verilog, and of just about
any other language, in its ability to sup****t this kind of
control.  Assignment overloading allows the programmer to
take *sub*type compatibility into account for assignment,
whereas the base language only considers *type* 
compatibility.  In an ideal world one could imagine the
ability to add user attributes that behave more like
built-in attributes - i.e. they propagate from actual to
formal parameters of a subprogram - so that a variable
could be tagged as "when assigning to me, do saturating 
overflow" or "when assigning to me, error out if my
(target) subtype doesn't match the expression's subtype".

>> Personally I think this leaves VHDL's fixed-point package
>> holed below the waterline; I would never use it on a 
>> serious project because of this risk of silent rescaling.

>I think no matter what you do there are issues to watch.

Fair enough.  I took care to qualify my statement with 
"personally" - others will surely see things differently.

>> Reason 2:  There are a few places in VHDL where you need a
>> boolean expression, but other kinds of expression would
>> make good sense.  For example:
>> 
>>   signal enable: std_logic;
>>   ...
>>   if enable then ...   -- currently illegal
>
>There is something for this already ("??").  Although := overloading
>could be made to work the same way.  There are lots of details.

OK.  Again there's some personal preference/prejudice at work 
here: I'm probably over-sensitive in my distaste for special-
purpose syntax designed to deal with a single issue.

Thanks for the sanity-check!
-- 
Jonathan Bromley, Consultant

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