Re: Signed, Unsigned syntax issues. Please help, I'm stumped

"Jim Lewis" <jim@[EMAIL PROTECTED]
> wrote in message 
news:48555383.1090500@[EMAIL PROTECTED]
> KJ,
>>> BTW, these are also in Accellera standard VHDL-2006-rev3.0, so
>>> if your vendors were looking out for your interests, they would
>>> have already should implemented these.
>>>
>>> Make sure to submit these as bug/enhancement requests.  This is 
>>> im****tant
>>> as this is what lets them know the VHDL community wants the new 
>>> features.
>>>
>>
>> I'll wait for one I like to see first.
>
> Don't hold your breath.
>

I never do, I find work arounds instead...much more effective than breath 
holding.

> The only way to get what you can live with (not necessarily even
> what you want) is to participate in the standards development.
>

I think you misinterpreted what I meant.  By saying "I'll wait for one I 
like to see first" I was simply stating that this particular member of the

VHDL community wasn't going to bug the vendors for *this* particular 
enhancement to be implemented since I just don't see myself using it for
the 
reasons that have been pointed out.  A new feature that I *am* interested
in 
using is something I would bug them for if it wasn't already implemented.

Presumably the indiviauals that thought the 'D' 'X' notation is what the 
VHDL world needs are the ones that should be voicing their needs if their 
tools don't sup****t it.

> Yacking out here is like screaming at a mountain.
>

Not really, it's an open forum to discuss problems that others might know
a 
solution for.  Kind of a pre-screening before submitting a bug/enhancement

request.  Sometimes the gripe ends in a legitimate enhancement request, 
sometimes it ends in the griper learning something they didn't know.

> P.S.
> If you are an expert VHDL coder there is no reason you should
> not be participating.

No idea whether I would qualify as an expert, but I can peruse Accelera
and 
see what the needs might be.

Kevin Jennings