Re: Signed, Unsigned syntax issues. Please help, I'm stumped

On Thu, 12 Jun 2008 14:02:55 +0100, Brian Drummond
<brian_drummond@[EMAIL PROTECTED]
> wrote:

>>What I mean...
>>  CTPBitCnt <= 1;
>>
>>What I have to write...
>>  CTPBitCnt <= to_unsigned(1, CTPBitCnt'length);
>>
>>Doesn't that seem a bit wordy?  I guess this example goes back to the
>>inability to overload the assignment operator which someone has
>>indicated may be changed in the next revision of the language.
>
>
>Ironically, thanks to overloaded operators,
>
>CTPBitCnt <= (others => '0') + 1;
>
>will work, and I would hope any synthesis tool would realise both inputs
>are constant.
>
>It's not pretty though...

Following on from this: (I apologise for not having tried it; I have no
access to a simulator at the moment)

Overload the unary "+" operator. This is commonly done in Ada for
various purposes; I don't see why it won't work in VHDL.

If so, then it ought to be possible to make 
CTPBitCnt <= +1;
work.

subtype BitCntType is ...

signal CTPBitCnt : BitCntType;

function "+" (int:integer) return BitCntType is
variable BitCnt:BitCntType := to_unsigned(int, BitCntType'length);
begin
    return BitCnt;
end function "+";

Offhand I don't see it working with unconstrained types like unsigned,
which makes it less attractive. Does anyone know better?

- Brian