Re: Signed, Unsigned syntax issues. Please help, I'm stumped

KJ
>>> I'll wait for one I like to see first.
>> Don't hold your breath.
>>
> 
> I never do, I find work arounds instead...much more effective than
breath 
> holding.
> 
>> The only way to get what you can live with (not necessarily even
>> what you want) is to participate in the standards development.
>>
> 
> I think you misinterpreted what I meant.  By saying "I'll wait for one I

> like to see first" I was simply stating that this particular member of
the 
> VHDL community wasn't going to bug the vendors for *this* particular 
> enhancement to be implemented since I just don't see myself using it for
the 
> reasons that have been pointed out.  A new feature that I *am*
interested in 
> using is something I would bug them for if it wasn't already
implemented.
> 
> Presumably the indiviauals that thought the 'D' 'X' notation is what the

> VHDL world needs are the ones that should be voicing their needs if
their 
> tools don't sup****t it.

Oops.  I must have overreacted.  This is exactly what I would ask all to
do - nag your vendor for the features you need and/or want.

>> P.S.
>> If you are an expert VHDL coder there is no reason you should
>> not be participating.
> 
> No idea whether I would qualify as an expert, but I can peruse Accelera
and 
> see what the needs might be.
My opinion is that anyone out here who is actively answering questions
would bring value to the standards groups.  Design expertise can help
weigh and understand language requests and feature implementations.
The group already has a number of members who are from eda vendors
and are LRM wizards (although there are room for more of these too).

Not sure if Accellera is willing to fund another round of revisions,
so it is likely the work will move back to IEEE and we will need to
put together a new funding model.

Cheers,
Jim