Re: simulation differences in modelsim

"jtw" <wrightjt @[EMAIL PROTECTED]
> wrote in message 
news:XZ%5k.1918$LG4.1333@[EMAIL PROTECTED]
> Alternatively, force the clock(s) to stop.  The simulation will stop
when 
> there are no more scheduled transactions.
>

In the current Modelsim and I believe ActiveHDL you can use the new
standard 
VHDL env package subprogram STOP/FINISH, example:

library std;
use std.env.all;

-- 0 prints nothing
-- 1 prints simulation time and location
-- 2 prints simulation time, location, and statistics about
--   the memory and CPU times used in simulation

STOP(1);

Which will result in a clean simulation stop:

# ** Note: stop
#    Time: 360 ns  Iteration: 0  Instance: /test_tb

Hans.
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