As commodity PC hardware and prouctivity applications deline in price, EDA
tools are as (relatively) expensive as ever, necessitating yet another
discussion of "Which simulator is right for me?"
The contendors are ...
1) Aldec Active-HDL
+ great design-flow assistants (state-diagram, block-diagram,
waveform-diagram editing, ex****t to PDF)
+ possibly faster than Modelsim/PE?
- no direct sup****t in FPGA design-suites (Webpack/Quartus)
- Windoze only (can WINE 1.0 run it?)
- Systemverilog is almost but not quite usable ('package' not
sup****ted?!?)
"less than $6000 for mixed-lang. VHDL+Verilog simulation"
(Note, that configuration is the most basic, doesn't have
SWIFT/Smartmodel)
[first year pepetual-license, yearly maint. is additional 20%/year]
2) Mentor Modelsim PE
+ currently more solid Systemverilog sup****t than Active-HDL,
(but limited to design-constructs, no assertions/coverage)
+ de-facto industry standard,
direct integration into FPGA design-suites (Webpack/Quartus)
+ SWIFT/Smartmodel sup****t (no extra cost if using mixed-HDL license)
- I really don't like the integrated waveform viewer
- Windoze only (can WINE 1.0 run it?)
"less than $10,000 for mixed-lang. VHDL+Verilog simulation"
[first year perpetual-license, yearly maint. is additional 20%/year]
3) FPGA-vendor OEM solution (usually a crippled Modelsim/PE)
+ cheapest
+ Altera Modelsim officially sup****ts Linux (Xilinx does not)
+ Xilinx Modelsim has same level of (design construct) Systemverilog
sup****t as Modelsim/PE, quite good actually
- limited capacity, deliberately slower runtime performance
- term-based only (no perpetual license for Xilinx/Altera?)
- no mixed-HDL (VHDL+Verilog) -- deal-killer for me...
"less than $1500 for 1-language, 1-year license"
If I only had to do 'abstract' RTL-design (algorithm proof, no
device-dependent instantiations...)
*4) gHDL, Icarus Verilog
+ free, open-source VHDL, Verilog
- emacs/gvim not included
- no mixed-HDL (VHDL+Verilog) sim
..............
Kidding aside, my real requirements:
1) I foresee mixed-HDL as a *requirement* for any serious consulting job.
(Xilinx and Altera are pretty good about providing 'HDL-neutral IP', but
third-parties aren't.)
2) ASIC sign-off is obviously not a concern -- who's going to compete with
a
professional turn-key bureau?
3) Design-size (capacity) is an unknown. For front-end (RTL) simulation,
I
think even the OEM Modelsims are adequate. But for gate-level, that might
push them over the limit. It's interesting that even a 'budget' <$500
FPGA-board already has sufficient gate-capacity to overwhelm a
single-designer...progress!
3) validation/qualification with fpga vendor. I like Active-HDL's
user-interface more than Modelsim, but I can't escape the fact that
Modelsim/PE has wider industry endorsement. It's hard to argue with the
management types who're more interested in checkboxes than the less
tangibles (oh ... like ... employee productivity?)
Finally, I note the irony of Modelsim/Altera and Modelsim/Xilinx editions.
Altera Quartus-II sup****ts Systemverilog synthesis, quite well, actually.
But Altera's Modelsim is based on the aging 6.1g version, which is
regrettably limited. Xilinx Webpack doesn't sup****t Systemverilog, but
their Modelsim/XE is based on the more recent 6.3c codebase. I find it
useful for testbenching, though too many colleagues heckle me for my
systemverilog "religion." (I believe in it, and so should they.)
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