Re: which commercial HDL-Simulator for FPGA?

In article <g3e8sk$ssv1@[EMAIL PROTECTED]
>,
Kevin Neilson  <kevin_neilson@[EMAIL PROTECTED]
> wrote:
>...  Modelsim is still the best, but you pay for a 
>lot of things you don't really need, and the waveform viewer could be 
>improved.  That's where you spend 90% of your time during debugging so 
>it should be a little easier to use.

I've used vcs and currently have access to ncsim, so I've not bothered
with
modelsim.  However, recently I tried the free one which comes with Altera
web edition.

So in either of these, you typically simulate and have all signals dumped
to
a huge output file (using $dumpvars(0); $dumpon; for vcs or
$shm_open(...);
$shm_probe(..); for ncsim).  Then you can explore the design hierarchy and
choose which signals to view in vcs -RPP or simvision.  The same is true
for
even icarus verilog with gtkwave.

However with modelsim it looks like there is no way to do this.  Instead,
when you add a signal to the viewer in the GUI, it re-runs the entire
simulation to get the new signal.  Am I missing something or is this
really
how it works?  I can't believe that it would really work this way.

(Also the crippled free modelsim is slower than icarus).

Has anyone tried to simulate Altera's IP with icarus?  I'm thinking about
the .vo simulation model of the altmemphy DDR controller.

-- 
/*  jhallen@[EMAIL PROTECTED]
 AB1GO */                        /* Joseph H.
Allen */
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