Re: which commercial HDL-Simulator for FPGA?

On 19 juin, 22:45, rickman <gnu...@[EMAIL PROTECTED]
> wrote:

> I use a purely HDL hierarchy.  I find that top level schematics or
> even low level schematics of large functions tend to end up being more
> like a net list than a drawing anyway.  You have pins with names X,Y,Z
> connected to net R,S,T on page 1.  On page 2 you have nets R,S,T
> connected to another part with pin names A,B,C.  Making it a drawing
> doesn't add much in my opinion.  Once I gave up hope for schematics
> and embraced the HDL world, I found joy in a life of text files and
> the infinite advantages they have in the land of version control!

I agree that a top level schematic is exactly like a netlist, but the
difference to me anyway is that I can quickly grasp how each blocks
are connected together. I try to keep most blocks on one large 11x17
page. Here's an example of what I mean:
http://www.yousendit.com/transfer.php?action=download&ufid=B152F0A35F44CD17

With a netlist, I have to read the several lines of vhdl code to
understand how the blocks are connected and that takes a longer time.
Ideally, the vhdl netlist is also accompanied by a block diagram. With
the schematics flow, the block diagram comes free.

The drawbacks of course are the version control problems associated
with schematics files and the lack of a standard file format. To me
the version control issues are not a big deal because all the meat is
in the vhdl blocks anyway, not the top level.

Patrick