Hello,
when writing FSMs (I like the 2 process approach) I find it convenient
to assign outputs directly in the different states. E.g. :
case current_state is
when state1 =>
data_out <= data_in1;
when state2 =>
data_out <= data_in2;
when state3....
-- some more states...
end case;
However, I've read somewhere (in the Xilinx timing improvement wizard,
I believe) that I should keep the dataflow out of the FSMs and use
control signals for the muxes instead.
To me this only seems like more typing and more signals in the design.
Will the synthesis tools (XST in my case) handle the two approaches
differently?
