Globally static expression

Hi,

I am using the following globally static expression:

CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND
cREGADDRGeneralRangeMask) IS
.....

When trying to compile that VHDL module with Modelsim I get the error
message:
Error: f:/sim/sim_msd/../../Src/Src_rtl/ProcInterface/
ProcInterface.vhd(930): (vcom-1014) Array type case expression must be
of a locally static subtype.

When putting it to synthesis with Synplify it is no problem at all.
Hardware is working fine.
So how can I solve that simulation "mismatch" ?

Rgds
Andre